(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a low-leakage shallow trench isolation (STI) in the fabrication of integrated circuits.
(2) Description of the Prior Art
As device technology is scaled down to the quarter micron regime and below, the use of the conventional local oxidation of silicon (LOCOS) isolation will be confined by smaller channel-width encroachment (bird's beak). Shallow trench isolation (STI) can be used to eliminate these encroachments, especially in ultra large scale integrated (ULSI) circuit devices.
However, in forming shallow trench isolation regions, after the trench has been filled, the removal of the pad oxide also results in the removal of the corner regions of the shallow trench isolation (STI) region causing corner recesses, as shown in FIG. 1. STI region 20 formed in the semiconductor substrate 10 has corner recesses 25. This results in a sharp corner 27 at the edge of the active area which will lead to a high electric field and leakage current. Polysilicon gate 30 is shown in a lateral view. When the polysilicon gate runs over the sharp corner 27 the high electric field problem occurs. This is also known as "poly wrap-around effect."
Also, this results in subthreshold humps in the MOS transistors formed in the active regions. The subthreshold hump 21 is an abnormal MOS device I.sub.D -V.sub.G curve caused by the high electric field built up at the sharp STI corner 27, as illustrated in FIG. 2. FIG. 2 illustrates gate electrode voltage V.sub.G as a function of saturation current I.sub.D. The high electric field results in the "V.sub.A -kmk" phenomenon, shown by 21, which results in a higher subthreshold leakage current and difficulty in controlling the threshold voltage.
A second problem is illustrated in FIG. 3. After silicidation 32 of the source/drain region 34, the recessed corners 25 allow junction leakage 35. A third problem occurs when forming a borderless contact, as shown in FIG. 4. Polysilicon contact 40 is formed over the STI region; resulting in gouging into the STI region and causing excessive contact leakage current 41.
A number of patents have addressed the formation of shallow trenches. U.S. Pat. No. 5,834,360 to Tesauro et al teaches etching a trench within a substrate, forming a silicon etch stop layer within the trench, and silicon nitride spacers on the sidewalls of the trench, and then oxidizing the silicon to form a field oxide region within the trench. U.S. Pat. No. 5,637,529 to Jang et al teaches forming silicon nitride spacers on the sidewalls of a patterned silicon nitride layer and then etching a trench into the substrate between the spacers. Germanium is ion implanted underlying the trench and a field oxidation region is formed within the trench. U.S. Pat. No. 5,780,325 to Lee forms an ion implanted region in a substrate, forms spacers on the sidewalls of an opening in an insulating layer over the implanted region, etches a trench through the implanted region, leaving implanted areas under the spacers at the sidewalls of the trench, and then fills the trench. U.S. Pat. No. 5,795,811 to Kim et al forms spacers on the sidewalls of an opening in an insulating layer and etches a trench between the spacers into the substrate. A two-step trench fill and etch back completes the isolation region. U.S. Pat. No. 5,753,562 to Kim teaches an STI method in which a trench is filled with layers of silicon nitride and oxide. The substrate is flipped over wherein the bottom of the trench becomes the top of the trench to prevent corner recesses.